The present invention relates to non-volatile memory array structures, and in preferred embodiments, particularly relates to those suitable for implementation of both memory and logic block structures.
Ongoing developments in semiconductor processing technologies and memory cell technologies continue to increase the density achieved in integrated circuit memory arrays. For example, certain passive element memory cell arrays may be fabricated having word lines approaching the minimum feature size (F) and minimum feature spacing for the particular word line interconnect layer, and also having bit lines approaching the minimum feature width and minimum feature spacing for the particular bit line interconnect layer. Moreover, three-dimensional memory arrays having more than one plane or level of memory cells have been fabricated implementing such so-called 4F2 memory cells on each memory plane. Exemplary three-dimensional memory arrays are described in U.S. Pat. No. 6,034,882 to Johnson, entitled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication,” and in U.S. Pat. No. 5,835,396 to Zhang, entitled “Three-Dimensional Read-Only Memory.”
A variety of other memory cell technologies and arrangements are also known. For example, NAND flash and NROM flash EEPROM memory arrays are also known to achieve relatively small memory cells. Other small flash EEPROM cells are known which use hot electron programming, such as NROM and floating gate NOR flash memory arrays. Such memory cells may also be desirable for a 3D memory array, although they frequently use many masks to produce a memory layer, and some use relatively high programming currents. Moreover, Ferro-electric (FeRAM) memory arrays are also known to produce relatively small memory cells.